The Polaris Single-FPGA Prototyping board solution can be used stand alone as an ASIC/SOC prototyping Appliance or in any host that has a PCI Express x8 slot via a PCI Express daughter card.

Configurations

The Single-FPGA Tile board comes in a single configuration: S4-Tile-V8S.

• S4-Tile-V8S has a nominal design capacity to accommodate up to 15 Million, 2-input NAND gate equivalent ASIC/SOC designs.

System Block Diagram

S4 Tile System Block Diagram

System Resources

The Tile board provides 5 HSMC connectors that have a total of 128 pins each, that can be configured as single ended, SERDES or LVDS pairs as per Altera HSMC specification. The Tile board also offers the following resources:

• 5 single ended global clocks (4 inputs, 1 on board oscillator)
• 4 single ended global clock outputs (can be driven from FPGA or forwarded clocks)
• 5 HSMC connectors – 4 type II connectors with 42, 1.65 Gbps LVDS pairs or 128 single ended; and 1 type I single-ended connectors
• 2 Differential clock outputs, 2 differential clock inputs per HSMC
• 1 Single ended clock input and 1 single ended clock output per HSMC
• Built in USB-based JTAG interface for programming
• 4 trigger outputs and 4 trigger inputs per system
• 1 Dual port, synchronous 18Mb SRAM

The following is included in the Tile board purchase:

• One year Time-based-license (TBL) of Altera Quartus II Fixed node, subscription edition (includes IP Base Suite and DSP Builder)
• USB Blaster Cable

The Tile board can be factory pre-configured with required daughter cards (Video, RF, I/O, Memory, USB, etc.) as a development kit. Please contact sales for details.

All Polaris products come with a 90-day product support and warranty. All Polaris products are protected by design and utility patents pending and issued.