As integrated circuit chips are becoming ever more complex, an entire electronic system is now designed onto a chip. In terms of size and complexity, what used to be an ASIC (Application Specific Integrated Circuit) just a few years ago is now a building block of a giant SoC (System on Chip). Typically, over 80% of an SoC is made up of existing design blocks. The remaining 20% are new functional blocks — often referred to as Design IP (Intellectual Property). Even when an SoC is designed from scratch, a majority of the effort is to assemble pre-built and pre-verified Design IPs and stitch them together with requisite glue logic. To thoroughly verify the functionality of an SoC, it is prudent to deploy software simulation, hardware emulation and ASIC prototyping at the appropriate phase of design.
As SoC complexity explodes in line with Moore’s law, unfortunately the functional RTL simulation environment has not kept pace with it. The processors inside massive servers have doubled in speed and capability over the past decade and there is certainly ample compute resource in terms of sheer number of machines in the server farm or the Cloud that the engineer has… Continue reading